A depiction of a network processing core 112 is shown in FIG. 1. A network processing core 112 is a circuit having a network processor 101 that is coupled to a data storage device (such as look-up resource 103 and memory unit 105). Network processors have received widespread attention recently because they integrate, onto a single semiconductor chip, circuitry that helps perform basic networking tasks. One basic networking task that a network processor 101 is commonly designed to help perform is a “look-up” based upon a packet's header information. The look up is typically performed to retrieve information that indicates how the packet is to be treated and/or classified.
For example, after a packet header or a portion of a portion of a packet header (either of which may be referred to as a header information unit or unit of header information) is presented to the network processor 101 at its input 102, the network processor 101 is responsible for understanding the organization of the header information unit so that at least a portion of it (e.g., its source address, its source port, its destination address, its destination port, a connection identifier, a classification identifier, some combination of any or all of these, etc.) can be used as a basis for performing a look-up. In various embodiments, a search key is formed by the network processor 101 from the header information unit. The search key, which acts as a look-up input parameter, is then presented to a look-up resource 103.
The look-up resource 103 stores information that is used by the network processor 101 to help “classify” the packet that the header information unit corresponds to. The look-up resource 103 can be implemented with a content addressable memory (CAM); and/or, a traditional memory such as a Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The look-up process may be performed, for each header information unit, with a single look-up (where the classification information is retrieved as an immediate response to the search key); or, alternatively a series of look-ups (e.g., a first look-up is performed from the search key to retrieve a reference value which; in turn, is used as a look-up parameter for a second look-up that produces the classification information).
According to at least one approach, the classification information that is obtained in response to the look-up performed by the network processor 101 is used by the network processor 101 to help treat the packet in an appropriate fashion. For example, the retrieved classification information may correspond to a “queue identifier” (or other form of information) that identifies (or helps to identify) a particular queue out of a plurality of queues that exist within memory unit 105. Memory unit 105 is typically implemented with SRAM or DRAM type memory. Here, the association of a particular packet with a particular queue serves as a vehicle for treating the packet in an appropriate fashion because differing amounts of delay are associated amongst the various queues that reside within the memory unit 105.
For example, differing rates of queue service may be implemented amongst the queues in order to implement “differentiated services” across the spectrum of packets that are presented to the network processor 101. For example, packets that should experience reduced latency (e.g., packets associated with a real time application such as a voice conversation or a video conference) may be placed into a queue that receives a high bandwidth rate of service (and therefore imposes reduced delay); and, packets that can experience a greater amount of latency (e.g., packets associated with a traditional data communication such as an email or a file transfer) may be placed into a queue that receives a low bandwidth rate of service (and therefore may impose extended periods of delay).
Once an appropriate time arises for a packet (or portion thereof) to be removed from its queue within the memory unit 105 (e.g., so that it can be transmitted onto an egress networking line or forwarded to a switching plane for transfer to another line interface card), it is read from memory unit 105 and is presented at the processor output 106 for downstream handling. Note that, in order to support this functionality, the network processor 101 can be designed to not only recognize that a plurality of queues exist within memory unit 105 but also determine when a packet (or portion thereof) is to be removed from the memory unit 105 (e.g., by not only recognizing where the different queues within memory unit 105 reside but also by implementing the particular service rates applied to each).
Here, note that the management and implementation of the queues within memory unit 105 may be viewed as a second basic networking task that the networking processor 101 is typically designed to help perform.